updated Thursday, July 29th, 1999

pstewart@gwi.net

Most of this is Julie S. Porter's work, though some of my application of the MN83803A chip will be reported as well to supplement her findings.

You may find her correspondence, in which she reports these findings, interesting, as it gives some idea of the inferential process we are applying, and some interesting context for the findings we present.

You may find it useful to remember, as you are reading the following notes, that the whole essence of what we are trying to do here is to get the MN83803AL to lock onto the sync signals we are applying to it (this being the key to the chip's function).

The design Julie uses matches Kristian Bognaes's design, drawn from that of the PV-D705 camcorder.

(1) Pin 41 ('S/V') determines the function of pin 6 (SYNC/VIDEO). High (5v) sets it to 'SYNC', low (0v) to 'VIDEO'.
(1.1) This also affects the polarity of the sync the chip expects.
(1.2) Putting the chip in 'VIDEO' mode by holding Pin 41 low, Julie was able to get the chip to lock onto the CD22402's -2.5 volt sync signal.
(1.3) When Pin 41 is held 'High', as in both the PV-D705 and PV-950B camcorder repair manuals, putting Pin 6 in SYNC mode, the chip takes a positive-going sync (see the voltage measurements given in these manuals).
(1.4) From this, we conclude that the S/V switch at Pin 41 determines what polarity the sync input at Pin 6 should be. When Pin 41 is held 'High', Pin 6 takes a positive-going SYNC signal; when it is held 'Low', Pin 6 takes a negative-going sync, supposedtly as part of the normal NTSC composite video signal, but, as Julie finds, requiring much larger magnitude than NTSC specifies. We will need to do more work to reconcile the experimental findings with the data sheets, but in the discussion that follows, we find some ideas about how to proceed.
(1.5) In the MN83803AK data sheets we find a 'measurement circuit' for sync functionality, in which the chip is set in VIDEO mode (S/V, Pin 41, held 'low') and a 'measurement timing' chart showing an apparently standard NTSC video signal; it is not stated where system ground is in this chart, but, like NTSC video, the composite signal is 1 volt peak-to-peak, with a sync depth of 0.3 volts (NTSC being 1V p-p with sync depth at -0.286 volts with respect to system ground).
(1.6) This is nominally consistent with Julie's results, in that the chip takes a negative sync while in 'VIDEO' mode. Obviously the magnitudes differ.
(1.7) Note that in the 'measurement circuit' diagram, the VIDEO input is capacitively coupled, with a 2.2 microfarad capacitor.

(2) 2V p-p negative was not quite enough to drive the sync. This stands against what the MN83803AK manual would suggest (-0.3V sync or 1Vp-p when in VIDEO mode).
(2.1) Julie got the chip to achieve lock (entrainment) to the sync input while in 'VIDEO' mode, pin 41 (S/V) held 'Low,' by applying -2.5V sync pulses from the CD22402 sync generator, and adjusting the 10k (centering) pot.
(2.2) Adjusting the 10k pot also varies the width of Hsync (at least when the MN83803AL is free-running).
(2.3) H pulses show up on the unconnected traces a little bit, apparently evidencing that our chip / board radiates quite a bit of EM.
(2.4) Julie found some noise on her input line (see below, in her correspondence). Is signal-to-noise ratio an issue with the chip's capacity to lock to sync? Obviously, in principle, 'yes'-- but in practice, does it affect our results at all?

(3) Julie used the same input conditioning circuit as the PV-D705 camcorder's and Kristian Bognaes's board that is derived from it. That camcorder holds Pin 41 (S/V) 'High', thereby setting Pin 6's (SYNC/VIDEO) function to 'SYNC', in keeping with the positive-going sync pulses the video processing chip's sync separator provides. SYNC goes directly from the video processing chip's sync separator to the MN83803AK's Pin 6 in this design (MN83803AL in Julie's present build of it). However, Julie was running the chip in VIDEO mode when she got it to lock onto its sync signal. The only application of the chip in VIDEO mode that we have documentation for is in the MN83803AK data sheets, in the 'measurement circuit' for sync separator function-- and in that circuit, as noted above in section (1.7), input to VIDEO (Pin 6) is coupled through a 2.2 microfarad capacitor.
(3.1) Therefore, some natural paths to explore would be to capacitively couple Pin 6 to straight NTSC video (or just NTSC-standard negative-going sync), while it is in VIDEO mode, and see if it will lock to sync; and to experiment further with positive-going sync while the chip is in SYNC mode (which one would expect would work better, since the PV-D705 is set up for this, and we are using the same input network).
(3.2) In general, it would be nice to know what kind of sync this chip really wants. In the service of this we have the definite knowledge that Julie's setup of the circuit with -2.5 volts sync, and Pin 6 in 'VIDEO' mode, works. We also see conditions of 0 volts and 5 volts shown for current flow in the MN83803AK's DC characteristics specifications-- suggesting that we will not destroy the chip if we keep within this range. (What are the most negative syncs we can apply without worry? And is the sync delivered by the IR3y05 sufficient? Is it ideal? Does the IR3y05y deliver a different sync amplitude?) We have the example, in the MN83803AK manual, of standard NTSC video going, capacitively coupled, into Pin 6 while it is in VIDEO mode (i.e. -0.286 volts sync tip). We don't really know where system ground is in that test signal diagram, but given Julie's success with a negative-going sync, we might well guess that the system ground is right where we would expect it to be for NTSC composite video.

(4) We choose to make S/V togglable between ground and +5V, so we can experiment with it.
(4.1) Therefore we pull this pin physically up from the p.c. board to get access to it, in our first designs based on the PV-D705 camcorder. (subsequent designs incorporate this functionality into the p.c. board, as you might hope)
(4.2) The pins are extremely delicate and easy to break; therefore there is no leeway to pull them this way and that; one must be careful to only bend them once, and carefully so as not to break them. I put a gob of epoxy on this pin to fix it to the chip after soldering a wire to it.
(4.3) The wire to use for this is #30 'blue wire'. You can get this ultrafine stuff at Jameco, for example.

(5) See our schematics page and for discussion of the apparent discrepancy between the sync voltage the IR3y05 delivers, and that which the MN83803AK is rated for. (Note that this may just arise from a typo in the Panasonic repair manual; also, the chip supplying sync in that circuit is not the IR3y05y, though the sync amplitude specified for the MN83803AK in that manual differs from what the IR3y05 is supposed to supply). We do not know if the IR3y05y delivers a different kind of sync from the IR3y05 (as for example it runs on a different voltage range), and we do not know precisely what differences there may be between the electrical characteristics of the MN83803AK and MN83803AL. Since Panasonic lists the latter as a pin-compatible substitute for the former, we may presume that it has precisely the same electrical characteristics, with some differences in logical functionality, or contains some change in design that does not render it incompatible with the -AK, at least in Panasonic designs. For this reason, inferences for the -AL are presumably good also for the -AK. We'll see-- as well for the plain -A variant, which is boxed as an -AK.

Julie's note regarding the MN83803AK, and getting it to lock onto a sync input

From - Wed May 05 13:01:15 1999


First about using the Hdrive/Vdrive. I was at work, I had left all the
paperwork at home. So I was working off memory. I had been reading some
video references on the sci.electronics.repair site. Some good stuff on how
a CRT works. And used those terms. Yes on the 83803AL these are labled H
Sync and V Sync. Pins 47 and 1.

The 83803AL is pretty resilient. I had put the 47uH inductor on the 14V
line. I did not have the filter caps as I was unsure if these were for the
LCD or not. The line was full of noise. However I could tell I had the chip
right way round. I added in the Caps. Now the work was to begin.

It is a good thing I built those other two video projects. This took every
bit of knowledge I gained. With the power on the chip I could see that while
a few lines looked soldered under the loupe: Signal was on the pin, but not
on the trace. I burned one trace off while attempting to reflow the line
next to it. This was awkward as other components blocked the iron. I got
this repaired.

Found that I had to do some of the output lines. Fortunately there were not
so many components in the way.

At this point I had all the expected signals on the lines. I connected sync
to the input. Nothing ...

I switched the resistors on the input to the way they were on Kristian's
board/PVD7054C.jpg. Still no lock.


Mystery #1 solved. This is a ground reference filter. I built this on the
alternate board (The one with the 44011) and measured the signal. I could
not tell if R942 was 10K/4.7/47K. I went with the latter as this gave the
cleanest ground reference on pin 5. This makes the ground ref that of video.
So we know know pin 5 is Video/Sync ground.

At this point I decided to beep out the chip. Beeping does run a small
voltage trough the tested area. I felt I had nothing to loose. I found that
the V1 and V2 grounds were not soldered down. Even though they looked that
way under the loupe. Still no sync lock.

I took some time out for dinner. I looked over the 83803A document again. I
found what I was looking for on page 9. (fig 1 circut diagram) has floating
above it the line S/V="L" just sitting there all alone. Now Pin 41 is
called S/V. On page 6 are some current requirements. The 4th column says
"L" Video input. "H" sync. Ahah I says to myself I'll bet SYNC is positive.
I looked up the IR3Y05 doc. Sure enough this is outputing positive sync.

Decision time. I decided to pull pin 41; I also had to re-work pin 39 as
they connect underneath. (It is really easy to burn off one of these small
traces)

Now pin 7 was high. Still no video lock. Adjusting the 10K pot (vr910,
centering) would cause the width of the H sync out to vary. I decided to
connect the sync from the CD22402 direct. It is somewhere around -2.5V. I
I tweaked the pot down, and the signal started to lock on.

Success. All the output signals look good. I can see the H phases. HT (FRP)
all locking to the input sync.

I have LC comm coming off the 14V supply. This is somewhere around 7V. This
is where the video needs to alternate about I would think. I have not
connected the LCD Panel yet. Nor have I set-up the Ground reference
circuits. I think the numbers next to the pins are voltage levels. I see
them really close to this. The HCPn lines swing somewhere in the 14V/18V
range. I wonder if the numbers shown on the 940/950 diagrams are RMS values? I
went to adjust the trigger in the scope and accidentally turned the supply
voltage up a volt. It did not seem to faze the thing. I am starting to
think that at least the AK can work at this.

The PV950-B: What I used may be for a 14V LCD. I have papers, papers
everywhere So I hope I have this right.

Now that I have this working I find I will need to start all over again.
Some of these control signals like S/V should be brought out so that they
can be grounded (or held high) to see what the different modes do. (You might want to watch
these when you put the chip down. Beware that it is expecting a positive
signal from the IR3y05. If this is pulled high then it could be switched so
different sync sources can be used. It might be better to go with the
IR3y05.

I want to stay with the video negative level as I have that on the 44011.
Next will be to try that and see if that locks. I should also see if the
backlight works off that part of the circuit.

-julieP